Memory state management for electronic device

ABSTRACT

In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described.

RELAYED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/795,439, filed on Mar. 12, 2013, now issued as U.S. Pat. No.9,454,214, which is incorporated herein by reference.

BACKGROUND

The subject matter described herein relates generally to the field ofelectronic devices and more particularly to a memory state managementfor electronic devices.

Mobile electronic devices such as, e.g., laptop computers, notebookcomputers, tablet computers, mobile phones, electronic readers, and thelike are commonly powered by one or more batteries. Many mobile devicesare rarely turned off. Rather, users allow the devices to enter a sleepstate in which various system components are placed in a low-activitystate for extended periods of time to save power. A memory system is oneof the consumers of power in an electronic device. Accordingly systemsand methods to manage memory systems may find utility.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is described with reference to the accompanyingfigures.

FIGS. 1 and 2 are high-level schematic illustrations of an electronicdevice which may be adapted to include battery power management inaccordance with some embodiments.

FIGS. 3 and 4 are schematic, block diagram illustration of components ofa memory system which may implement memory state management inaccordance with various embodiments discussed herein.

FIG. 5 is a flowchart illustrating operations in a method for batterypower management in accordance with some embodiments.

FIGS. 6-9 are schematic illustrations of electronic devices which may bemodified to implement battery power management in accordance with someembodiments.

DETAILED DESCRIPTION

Described herein are exemplary systems and methods to implement memorystate management in electronic devices. Memory systems may include avolatile memory such as Dynamic Random Access Memory (DRAM), whichfrequently functions as cache memory, and nonvolatile memory such asphase change memory, NAND memory or the like or even magnetic or opticalmemory. Volatile memory generally exhibits faster response times (i.e.,lower latency) but consumes more power, at least in part due to refreshrequirements. During operation of the electronic device it may bebeneficial to store data in DRAM memory for highest possible memorybandwidth. However there may be long periods of time when an electronicdevice is not under heavy use. During periods of inactivity it may bebeneficial to implement memory state management to manage memoryoperations in a way that balances performance requirements with powerconservation.

In a two level memory (2LM) the physical memory address space is mappedto a nonvolatile memory. There is also a large volatile memory (i.e.,DRAM) cache to keep performance high, as the nonvolatile memorytechnology has higher latency and lower bandwidth than standard DRAM.The nonvolatile memory consumes little power at idle, unlike DRAM, whichconsumes considerable power during idle. In embodiments described hereinrelatively more data is kept in the DRAM under heavy load and less datain DRAM during low utilization. In each case all data is kept in thenonvolatile memory store, but the size of the DRAM cache may be adjustedto save power.

DRAM memory is generally managed using memory tables which map logicaladdresses onto the underlying physical memory structure and whichmaintain state information about the memory. Example states are modified(M), Exclusive (E), shared (S), and invalid (I). In accordance withembodiments described herein a new memory state unused (U) isintroduced. Memory may be placed into the U state when the electronicdevice is in a low activity state. When memory is placed in a U state,the DRAM cache size can be reduced either by suspending refreshoperations to memory in the U state or by writing data from the volatilememory back to the nonvolatile memory and then powering down thevolatile memory.

Thus, when an electronic device is in a low-activity state (e.g., asleep state) the memory system may suspend operations of some or all ofthe volatile memory in order to conserve power. In some embodiments theamount of volatile memory that is suspended may be managed dynamicallyby setting a threshold target for a performance parameter such as thecache miss rate. If the cache miss rate is below a threshold thenadditional volatile memory may be taken off line to conserve power. Bycontrast, if the cache miss rate exceeds a threshold then volatilememory may be brought back online.

In the following description, numerous specific details are set forth toprovide a thorough understanding of various embodiments. However, itwill be understood by those skilled in the art that the variousembodiments may be practiced without the specific details. In otherinstances, well-known methods, procedures, components, and circuits havenot been illustrated or described in detail so as not to obscure theparticular embodiments.

FIG. 1 is a schematic illustration of an exemplary electronic device 100which may be adapted to implement battery power management as describedherein, in accordance with some embodiments. In one embodiment,electronic device 100 includes one or more accompanying input/outputdevices including a display 102 having a screen 104, one or morespeakers 106, a keyboard 110, and a mouse 114. In various embodiments,the electronic device 100 may be embodied as a personal computer, alaptop computer, a personal digital assistant, a mobile telephone, anentertainment device, or another computing device.

The electronic device 100 includes system hardware 120 and memory 130,which may be implemented as random access memory and/or read-onlymemory. A power source such as a battery 180 may be coupled to theelectronic device 100.

System hardware 120 may include one or more processors 122, one or moregraphics processors 124, network interfaces 126, and bus structures 128.In one embodiment, processor 122 may be embodied as an Intel ® Core2Duo® processor available from Intel Corporation, Santa Clara, Calif.,USA. As used herein, the term “processor” means any type ofcomputational element, such as but not limited to, a microprocessor, amicrocontroller, a complex instruction set computing (CISC)microprocessor, a reduced instruction set (RISC) microprocessor, a verylong instruction word (VLIW) microprocessor, or any other type ofprocessor or processing circuit.

Graphics processor(s) 124 may function as adjunct processor that managesgraphics and/or video operations. Graphics processor(s) 124 may beintegrated onto the motherboard of electronic device 100 or may becoupled via an expansion slot on the motherboard.

In one embodiment, network interface 126 could be a wired interface suchas an Ethernet interface (see, e.g., Institute of Electrical andElectronics Engineers/IEEE 802.3-2002) or a wireless interface such asan IEEE 802.11a, b or g-compliant interface (see, e.g., IEEE Standardfor IT-Telecommunications and information exchange between systemsLAN/MAN—Part II: Wireless LAN Medium Access Control (MAC) and PhysicalLayer (PHY) specifications Amendment 4: Further Higher Data RateExtension in the 2.4 GHz Band, 802.11G-2003). Another example of awireless interface would be a general packet radio service (GPRS)interface (see, e.g., Guidelines on GPRS Handset Requirements, GlobalSystem for Mobile Communications/GSM Association, Ver. 3.0.1, December2002).

Bus structures 128 connect various components of system hardware 128. Inone embodiment, bus structures 128 may be one or more of several typesof bus structure(s) including a memory bus, a peripheral bus or externalbus, and/or a local bus using any variety of available bus architecturesincluding, but not limited to, 11-bit bus, Industrial StandardArchitecture (ISA), Micro-Channel Architecture (MSA), Extended ISA(EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB),Peripheral Component Interconnect (PCI), Universal Serial Bus (USB),Advanced Graphics Port (AGP), Personal Computer Memory CardInternational Association bus (PCMCIA), and Small Computer SystemsInterface (SCSI).

Memory 130 may store an operating system 140 for managing operations ofelectronic device 100. In one embodiment, operating system 140 includesa hardware interface module 154, e.g., a device driver, that provides aninterface to system hardware 120. In addition, operating system 140 mayinclude a file system 150 that manages files used in the operation ofelectronic device 100 and a process control subsystem 152 that managesprocesses executing on electronic device 100.

Operating system 140 may include (or manage) one or more communicationinterfaces that may operate in conjunction with system hardware 120 totransceive data packets and/or data streams from a remote source.Operating system 140 may further include a system call interface module142 that provides an interface between the operating system 140 and oneor more application modules resident in memory 130. Operating system 140may be embodied as a UNIX operating system or any derivative thereof(e.g., Linux, Solaris, etc.) or as a Windows® brand operating system, orother operating systems.

In some embodiments memory 130 may store one or more applications whichmay execute on the one or more processors 122 including a state manage162. These applications may be embodied as logic instructions stored ina tangible, non-transitory computer readable medium (i.e., software orfirmware) which may be executable on one or more of the processors 122.Alternatively, these applications may be embodied as logic on aprogrammable device such as a field programmable gate array (FPGA) orthe like. Alternatively, these applications may be reduced to logic thatmay be hardwired into an integrated circuit.

In some embodiments electronic device 100 may comprise a low-powerembedded processor, referred to herein as a controller 170. Thecontroller 170 may be implemented as an independent integrated circuitlocated on the motherboard of the system 100. In some embodiments thecontroller 170 may comprise one or more processors 172 and a memorymodule 174, and the state manager 162 may be implemented in thecontroller 170. By way of example, the memory module 174 may comprise apersistent flash memory module and the state manager 162 may beimplemented as logic instructions encoded in the persistent memorymodule, e.g., firmware or software. Because the controller 170 isphysically separate from the main processor(s) 122 and operating system140, the adjunct controller 170 may be made secure, i.e., inaccessibleto hackers such that it cannot be tampered with.

FIG. 2 is a schematic illustration of another embodiment of anelectronic device 200 which may be adapted to which may be adapted toimplement battery power management as described herein, according toembodiments. In some embodiments electronic device 200 may be embodiedas a mobile telephone, a personal digital assistant (PDA), a laptopcomputer, or the like. Electronic device 200 may include one or moretemperature sensors 212, an RF transceiver 220 to transceive RF signalsand a signal processing module 222 to process signals received by RFtransceiver 220.

RF transceiver 220 may implement a local wireless connection via aprotocol such as, e.g., Bluetooth or 802.11X. IEEE 802.11a, b org-compliant interface (see, e.g., IEEE Standard forIT-Telecommunications and information exchange between systemsLAN/MAN—Part II: Wireless LAN Medium Access Control (MAC) and PhysicalLayer (PHY) specifications Amendment 4: Further Higher Data RateExtension in the 2.4 GHz Band, 802.11G-2003). Another example of awireless interface would be a general packet radio service (GPRS)interface (see, e.g., Guidelines on GPRS Handset Requirements, GlobalSystem for Mobile Communications/GSM Association, Ver. 3.0.1, December2002).

Electronic device 200 may further include one or more processors 224 anda memory module 240. As used herein, the term “processor” means any typeof computational element, such as but not limited to, a microprocessor,a microcontroller, a complex instruction set computing (CISC)microprocessor, a reduced instruction set (RISC) microprocessor, a verylong instruction word (VLIW) microprocessor, or any other type ofprocessor or processing circuit. In some embodiments, processor 224 maybe one or more processors in the family of Intel® PXA27x processorsavailable from Intel® Corporation of Santa Clara, Calif. Alternatively,other CPUs may be used, such as Intel's Itanium®, XEON™, ATOM™, andCeleron® processors. Also, one or more processors from othermanufactures may be utilized. Moreover, the processors may have a singleor multi core design.

In some embodiments, memory module 240 includes volatile memory (RAM);however, memory module 240 may be implemented using other memory typessuch as dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like.Memory 240 may store one or more applications which execute on theprocessor(s) 222.

Electronic device 200 may further include one or more input/outputinterfaces such as, e.g., a keypad 226 and one or more displays 228. Insome embodiments electronic device 200 comprises one or more cameramodules 220 and an image signal processor 232, and speakers 234. A powersource such as a battery 270 may be coupled to electronic device 200.

In some embodiments electronic device 200 may include a controller 270which may be implemented in a manner analogous to that of adjunctcontroller 170, described above. In the embodiment depicted in FIG. 2the controller 270 comprises one or more processor(s) 272 and a memorymodule 274, which may be implemented as a persistent flash memorymodule. Because the controller 270 is physically separate from the mainprocessor(s) 224, the controller 270 may be made secure, i.e.,inaccessible to hackers such that it cannot be tampered with.

In some embodiments at least one of the memory 230 or the controller 270may comprise a state manager 162, which may be implemented as logicinstructions encoded in the persistent memory module, e.g., firmware orsoftware.

FIG. 3 is a schematic, block diagram illustration of components ofapparatus to implement memory latency management in accordance withvarious embodiments discussed herein. Referring to FIG. 3, in someembodiments a central processing unit (CPU) package 300 which maycomprise one or more CPUs 310 coupled to a control hub 320 and a localmemory 330. Control hub 320 comprises a memory controller 322 and amemory interface 324.

Memory interface 324 is coupled to one or more remote memory devices 340by a communication bus 360. Memory device 340 may comprise a controller342 and one or more memory banks 350. In various embodiments, memorybanks 350 may be implemented using nonvolatile memory. By way ofexample, in some embodiments the memory device(s) 340 may comprise anysuitable non-volatile memory, including but not limited to NAND (flash)memory, ferroelectric random-access memory (FeTRAM), nanowire-basednon-volatile memory, memory that incorporates memristor technology,MRAM, STT-MRAM, three dimensional (3D) cross point resistive memory suchas phase change memory (PCM). The specific configuration of the memorybank(s) 350 in the memory device(s) 340 is not critical.

In various embodiments, memory 330 may be implemented using volatilememory such as one or more DRAM memory modules. FIG. 4 is a schematic,block diagram of an exemplary 330 which may be adapted to implementmemory state management in accordance with various embodiments discussedherein. Referring to FIG. 4, in some embodiments the memory 330 maycomprise one or more direct in-line memory modules (DIMMs) 450 coupledto a memory channel 470 which provides a communication link to memorycontroller 322. In the embodiment depicted in FIG. 4 each DIMM comprisesa first rank 455 and a second rank 460, each of which includes aplurality of DRAM modules 465. One skilled in the art will recognizethat memory 330 may comprise more or fewer DIMMs 450, and more or fewerranks per DIMM. Further, some electronic devices (e.g., smart phones,tablet computers, and the like) may comprise simpler memory systemscomprised of one or more DRAMs which need not be organized into DIMMs.

Having described various embodiments and configurations of electronicdevices which may be adapted to implement memory state management,attention will now be turned to methods to implement memory statemanagement. In some embodiments the state manager 162 may comprise logicwhich, when executed, implements memory state management in a memorysystem of an electronic device. Operations of the state manager 162 willbe described with reference to FIG. 5.

Referring to FIG. 5, at operation 510 the state manager 162 monitors thedevice state. Many computer systems and their respective components mayoperate in one of a plurality of power states. By way of example, theAdvanced Configuration and Power Interface (ACPI) specification definesa plurality of active states and a plurality of inactive, or sleep,states for electronic devices. Each state is associated with particularoperating states for various components and thereby defines differentpower consumption states. Sleep states are numbered S1-S4 states. Highernumbers correlate to deeper sleep states and correspondingly lower powerconsumption. By way of example, the state manager 162 may periodicallycheck the sleep state from the ACPI register maintained by the basicinput/output system (BIOS) of the electronic device.

If, at operation 515, the electronic device is not in a low power (i.e.,sleep) state then control passes back to operation 510 and normal memoryoperations are allowed to continue. By contrast, if at operation 515 thedevice is in a low power state then the state manager 162 implements amemory state management routine which reduces power to at least asection of volatile memory in the memory 330. In some embodiments thestate manager 162 may require the electronic device to be in a specifiedsleep state (e.g., S3) or higher in order to invoke a memory statemanagement routine.

At operation 520 the state manager 162 suspends refresh operations tosections of the volatile memory in memory 330. By way of example, insome embodiments the state manager 162 may scan one or more memorymanagement tables associated with the volatile memory in memory 330 andmay identify one or more sections (e.g., cache lines, pages, or entireDRAMS) which are in an I state. The state manager 162 may then instructthe memory controller 322 to skip refresh operations on some or all ofthe memory sections identified as being in the I state.

At operation 525 the state manager 162 may relocate data from one ormore sections of the volatile memory in memory 330. By way of example,in some embodiments the state manager 162 may scan one or more memorymanagement tables associated with the volatile memory in volatile memory330 and may identify one or more sections (e.g., cache lines, pages, orentire DRAMS) which are in an M state. The state manager 162 may theninstruct the memory controller 322 to relocate the data, e.g., bywriting the data back to nonvolatile memory in volatile memory device(s)340. In some examples this may be performed at the DRAM level so thatall data from sections in an M state on a DRAM is written back to thenonvolatile memory in volatile memory device(s) 340. The state managermay then cut power (operation 530) to the DRAM chip, taking the DRAMchip offline.

When the memory system is operating in a state with reduced volatilememory capacity the state manager 162 may implement a routine whichadjusts the amount of active nonvolatile memory dynamically in responseto changes in the cache miss rate to achieve a balance betweenperformance requirements and power conservation. Thus, at operation 535the state manager 162 monitors the cache miss rate of the memory 330.

If at operation 540 the cache miss rate is less than a threshold valuethen the state manager 162 will attempt to take more volatile memoryoffline to conserve power. Control thus passes to operation 545 and thestate manager 162 may locate the least recently used (LRU) blocks ofvolatile memory in memory 330. At operation 550 the state manager 162collects active pages of memory onto a subset of DIMMs in the volatilememory 330. At operation 555 the state manager 162 transitions the leastrecently used pages to an unused (U) state, and at operation 560 thestate manager 162 powers down the DRAM chip. Control can then pass backto operation 535 and state manager 162 continues to monitor the cachemiss rate.

If, at operation 540 the cache miss rate is not less than a thresholdvalue, then control passes to operation 565. If, at operation 565 thereare no DRAMs powered off then control passes back to operation 535 andthe state manager 162 continues to monitor the cache miss rate. Bycontrast, if at operation 570 one or more DRAMs are powered off thencontrol passes to operation 570 and the state manager 162 activates aportion of the volatile memory to increase the amount of volatile memoryavailable in memory 330. To activate the volatile memory the statemanager 162 may identify regions of memory to bring back online and mayset the memory back into a self-refresh mode. The cache state for thememory may then be transitioned from the unused (U) state to the invalid(I) state.

Thus, operations 535-570 define a loop by which the state manager 162can dynamically adjust the amount of volatile memory available in memory330 to strike a balance between memory performance and power consumptionwhen the memory 330 is operating in a reduced capacity. In someembodiments the state manager may utilize information from page tablesfor memory 330 to facilitate operations. For example, pages that aremapped as read-only, such as executable pages, can be placed in an areaof contiguous memory such that the state manager 162 does not have tolook for modified lines (M state). Rather, it can transition directlyfrom state X to state U with no write back operations required. Thissaves power since no volatile memory writes will be required. Theoperating system memory manager may also be arranged such that read-onlypages are located contiguously.

As described above, in some embodiments the electronic device may beembodied as a computer system. FIG. 6 illustrates a block diagram of acomputing system 600 in accordance with an embodiment of the invention.The computing system 600 may include one or more central processingunit(s) (CPUs) 602 or processors that communicate via an interconnectionnetwork (or bus) 604. The processors 602 may include a general purposeprocessor, a network processor (that processes data communicated over acomputer network 603), or other types of a processor (including areduced instruction set computer (RISC) processor or a complexinstruction set computer (CISC)). Moreover, the processors 602 may havea single or multiple core design. The processors 602 with a multiplecore design may integrate different types of processor cores on the sameintegrated circuit (IC) die. Also, the processors 602 with a multiplecore design may be implemented as symmetrical or asymmetricalmultiprocessors. In an embodiment, one or more of the processors 602 maybe the same or similar to the processors 102 of FIG. 1. For example, oneor more of the processors 602 may implement the state manager discussedwith reference to FIGS. 1-2. Also, the operations discussed withreference to FIG. 5 may be performed by one or more components of thesystem 600.

A chipset 606 may also communicate with the interconnection network 604.The chipset 606 may include a memory control hub (MCH) 608. The MCH 608may include a memory controller 610 that communicates with a memory 612(which may be the same or similar to the memory 130 of FIG. 1). Thememory 412 may store data, including sequences of instructions, that maybe executed by the CPU 602, or any other device included in thecomputing system 600. In one embodiment of the invention, the memory 612may include one or more volatile storage (or memory) devices such asrandom access memory (RAM), dynamic RAM (DRAM), synchronous DRAM(SDRAM), static RAM (SRAM), or other types of storage devices.Additional devices may communicate via the interconnection network 604,such as multiple CPUs and/or multiple system memories.

The MCH 608 may also include a graphics interface 614 that communicateswith a display device 616. In one embodiment of the invention, thegraphics interface 614 may communicate with the display device 616 viaan accelerated graphics port (AGP). In an embodiment of the invention,the display 616 (such as a flat panel display) may communicate with thegraphics interface 614 through, for example, a signal converter thattranslates a digital representation of an image stored in a storagedevice such as video memory or system memory into display signals thatare interpreted and displayed by the display 616. The display signalsproduced by the display device may pass through various control devicesbefore being interpreted by and subsequently displayed on the display616.

A hub interface 618 may allow the MCH 608 and an input/output controlhub (ICH) 620 to communicate. The ICH 620 may provide an interface toI/O device(s) that communicate with the computing system 600. The ICH620 may communicate with a bus 622 through a peripheral bridge (orcontroller) 624, such as a peripheral component interconnect (PCI)bridge, a universal serial bus (USB) controller, or other types ofperipheral bridges or controllers. The bridge 624 may provide a datapath between the CPU 602 and peripheral devices. Other types oftopologies may be utilized. Also, multiple buses may communicate withthe ICH 620, e.g., through multiple bridges or controllers. Moreover,other peripherals in communication with the ICH 620 may include, invarious embodiments of the invention, integrated drive electronics (IDE)or small computer system interface (SCSI) hard drive(s), USB port(s), akeyboard, a mouse, parallel port(s), serial port(s), floppy diskdrive(s), digital output support (e.g., digital video interface (DVI)),a solid state drive (SSD) with SATA interface or PCIe interface, orother devices.

The bus 622 may communicate with an audio device 626, one or more diskdrive(s) 628, and a network interface device 630 (which is incommunication with the computer network 603). Other devices maycommunicate via the bus 622. Also, various components (such as thenetwork interface device 630) may communicate with the MCH 608 in someembodiments of the invention. In addition, the processor 602 and one ormore other components discussed herein may be combined to form a singlechip (e.g., to provide a System on Chip (SOC)). Furthermore, thegraphics accelerator 616 may be included within the MCH 608 in otherembodiments of the invention.

Furthermore, the computing system 600 may include volatile and/ornonvolatile memory (or storage). For example, nonvolatile memory mayinclude one or more of the following: read-only memory (ROM),programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM(EEPROM), a disk drive (e.g., 628), a floppy disk, a compact disk ROM(CD-ROM), a digital versatile disk (DVD), flash memory, amagneto-optical disk, or other types of nonvolatile machine-readablemedia that are capable of storing electronic data (e.g., includinginstructions).

FIG. 7 illustrates a block diagram of a computing system 700, accordingto an embodiment of the invention. The system 700 may include one ormore processors 702-1 through 702-N (generally referred to herein as“processors 702” or “processor 702”). The processors 702 may communicatevia an interconnection network or bus 704. Each processor may includevarious components some of which are only discussed with reference toprocessor 702-1 for clarity. Accordingly, each of the remainingprocessors 702-2 through 702-N may include the same or similarcomponents discussed with reference to the processor 702-1.

In an embodiment, the processor 702-1 may include one or more processorcores 706-1 through 706-M (referred to herein as “cores 706” or moregenerally as “core 706”), a shared cache 708, a router 710, and/or aprocessor control logic or unit 720. The processor cores 706 may beimplemented on a single integrated circuit (IC) chip. Moreover, the chipmay include one or more shared and/or private caches (such as cache708), buses or interconnections (such as a bus or interconnectionnetwork 712), memory controllers, or other components.

In one embodiment, the router 710 may be used to communicate betweenvarious components of the processor 702-1 and/or system 700. Moreover,the processor 702-1 may include more than one router 710. Furthermore,the multitude of routers 710 may be in communication to enable datarouting between various components inside or outside of the processor702-1.

The shared cache 708 may store data (e.g., including instructions) thatare utilized by one or more components of the processor 702-1, such asthe cores 706. For example, the shared cache 708 may locally cache datastored in a memory 714 for faster access by components of the processor702. In an embodiment, the cache 708 may include a mid-level cache (suchas a level 2 (L2), a level 3 (L3), a level 4 (L4), or other levels ofcache), a last level cache (LLC), and/or combinations thereof. Moreover,various components of the processor 702-1 may communicate with theshared cache 708 directly, through a bus (e.g., the bus 712), and/or amemory controller or hub. As shown in FIG. 7, in some embodiments, oneor more of the cores 706 may include a level 1 (L1) cache 716-1(generally referred to herein as “L1 cache 716”). In one embodiment, thecontroller 720 may include logic to implement the operations describedabove with reference to FIG. 3.

FIG. 8 illustrates a block diagram of portions of a processor core 706and other components of a computing system, according to an embodimentof the invention. In one embodiment, the arrows shown in FIG. 8illustrate the flow direction of instructions through the core 706. Oneor more processor cores (such as the processor core 706) may beimplemented on a single integrated circuit chip (or die) such asdiscussed with reference to FIG. 7. Moreover, the chip may include oneor more shared and/or private caches (e.g., cache 708 of FIG. 7),interconnections (e.g., interconnections 704 and/or 112 of FIG. 7),control units, memory controllers, or other components.

As illustrated in FIG. 8, the processor core 706 may include a fetchunit 802 to fetch instructions (including instructions with conditionalbranches) for execution by the core 706. The instructions may be fetchedfrom any storage devices such as the memory 714. The core 706 may alsoinclude a decode unit 804 to decode the fetched instruction. Forinstance, the decode unit 804 may decode the fetched instruction into aplurality of uops (micro-operations).

Additionally, the core 706 may include a schedule unit 806. The scheduleunit 806 may perform various operations associated with storing decodedinstructions (e.g., received from the decode unit 804) until theinstructions are ready for dispatch, e.g., until all source values of adecoded instruction become available. In one embodiment, the scheduleunit 806 may schedule and/or issue (or dispatch) decoded instructions toan execution unit 808 for execution. The execution unit 808 may executethe dispatched instructions after they are decoded (e.g., by the decodeunit 804) and dispatched (e.g., by the schedule unit 806). In anembodiment, the execution unit 808 may include more than one executionunit. The execution unit 808 may also perform various arithmeticoperations such as addition, subtraction, multiplication, and/ordivision, and may include one or more an arithmetic logic units (ALUs).In an embodiment, a co-processor (not shown) may perform variousarithmetic operations in conjunction with the execution unit 808.

Further, the execution unit 808 may execute instructions out-of-order.Hence, the processor core 706 may be an out-of-order processor core inone embodiment. The core 706 may also include a retirement unit 810. Theretirement unit 810 may retire executed instructions after they arecommitted. In an embodiment, retirement of the executed instructions mayresult in processor state being committed from the execution of theinstructions, physical registers used by the instructions beingde-allocated, etc.

The core 706 may also include a bus unit 714 to enable communicationbetween components of the processor core 706 and other components (suchas the components discussed with reference to FIG. 8) via one or morebuses (e.g., buses 804 and/or 812). The core 706 may also include one ormore registers 816 to store data accessed by various components of thecore 706 (such as values related to power consumption state settings).

Furthermore, even though FIG. 7 illustrates the control unit 720 to becoupled to the core 706 via interconnect 812, in various embodiments thecontrol unit 720 may be located elsewhere such as inside the core 706,coupled to the core via bus 704, etc.

In some embodiments, one or more of the components discussed herein canbe embodied as a System On Chip (SOC) device. FIG. 9 illustrates a blockdiagram of an SOC package in accordance with an embodiment. Asillustrated in FIG. 9, SOC 902 includes one or more Central ProcessingUnit (CPU) cores 920, one or more Graphics Processor Unit (GPU) cores930, an Input/Output (I/O) interface 940, and a memory controller 942.Various components of the SOC package 902 may be coupled to aninterconnect or bus such as discussed herein with reference to the otherfigures. Also, the SOC package 902 may include more or less components,such as those discussed herein with reference to the other figures.Further, each component of the SOC package 902 may include one or moreother components, e.g., as discussed with reference to the other figuresherein. In one embodiment, SOC package 902 (and its components) isprovided on one or more Integrated Circuit (IC) die, e.g., which arepackaged into a single semiconductor device.

As illustrated in FIG. 9, SOC package 902 is coupled to a memory 960(which may be similar to or the same as memory discussed herein withreference to the other figures) via the memory controller 942. In anembodiment, the memory 960 (or a portion of it) can be integrated on theSOC package 902.

The I/O interface 940 may be coupled to one or more I/O devices 970,e.g., via an interconnect and/or bus such as discussed herein withreference to other figures. I/O device(s) 970 may include one or more ofa keyboard, a mouse, a touchpad, a display, an image/video capturedevice (such as a camera or camcorder/video recorder), a touch screen, aspeaker, or the like.

The following examples pertain to further embodiments.

Example 1 is a computer program product comprising logic instructionsstored in a non-transitory computer readable medium which, when executedby a controller, configure the controller to perform operations tomanage a memory state of a volatile memory, comprising determiningwhether an electronic device comprising a volatile memory and anonvolatile memory is operating in a low power state, and in response toa determination that the electronic device is operating in a low powerstate, implementing a memory state management routine which reducespower to at least a section of the volatile memory in the memory system.

The computer program product may further comprising logic instructionsstored in the non-transitory computer readable medium which, whenexecuted by the controller, configure the controller to performoperations comprising identifying one or more sections of volatilememory which are in an invalid state and suspending refresh operationsto the one or more sections of volatile memory in an invalid state.

The computer program product may further comprise logic instructionsstored in the non-transitory computer readable medium which, whenexecuted by the controller, configure the controller to performoperations comprising identifying one or more sections of a volatilememory module which are in a modified state, relocating data from theone or more sections of a volatile memory module which are in a modifiedstate, and powering down the volatile memory module.

The computer program product may further comprise logic instructionsstored in the non-transitory computer readable medium which, whenexecuted by the controller, configure the controller to performoperations comprising determining whether a cache miss rate is below athreshold and in response to a determination that the cache miss rate isbelow the threshold identifying one or more least recently used sectionsof a volatile memory module which are in a modified state relocatingdata from the one or more least recently used sections of the volatilememory module which are in a modified state and powering down thevolatile memory module.

The computer program product may further comprise logic instructionsstored in the non-transitory computer readable medium which, whenexecuted by the controller, configure the controller to performoperations comprising determining whether a cache miss rate is below athreshold and in response to a determination that the cache miss rate isnot below the threshold activating at least one inactive memory module.

The sections of volatile memory correspond to at least one of a cacheline, a memory chip, a memory rank, or a memory bank.

In example 2, a controller comprises logic to determine whether anelectronic device comprising a volatile memory and a nonvolatile memoryis operating in a low power state and in response to a determinationthat the electronic device is operating in a low power state, implementa memory state management routine which reduces power to at least asection of the volatile memory in the memory system.

The controller may comprise logic to identify one or more sections ofvolatile memory which are in an invalid state and suspend refreshoperations to the one or more sections of volatile memory in an invalidstate.

The controller may comprise logic to identify one or more sections of avolatile memory module which are in a modified state relocate data fromthe one or more sections of a volatile memory module which are in amodified state, and power down the volatile memory module.

The controller may comprise logic to determine whether a cache miss rateis below a threshold, and in response to a determination that the cachemiss rate is below the threshold, to identify one or more least recentlyused sections of a volatile memory module which are in a modified state,relocate data from the one or more least recently used sections of thevolatile memory module which are in a modified state, and power down thevolatile memory module.

The controller may comprise logic to determine whether a cache miss rateis below a threshold, and in response to a determination that the cachemiss rate is not below the threshold, to activate at least one inactivememory module.

The sections of volatile memory correspond to at least one of a cacheline, a memory chip, a memory rank, or a memory bank.

In example 3, an electronic device, comprises a memory system and acontroller comprising logic to determine whether an electronic device isoperating in a low power state, and in response to a determination thatthe electronic device is operating in a low power state, implement amemory state management routine which reduces power to at least asection of volatile memory in the memory system.

The electronic device may comprise logic to identify one or moresections of volatile memory which are in an invalid state, and suspendrefresh operations to the one or more sections of volatile memory in aninvalid state.

The electronic device may comprise logic to identify one or moresections of a volatile memory module which are in a modified state,relocate data from the one or more sections of a volatile memory modulewhich are in a modified state, and power down the volatile memorymodule.

The electronic device may comprise logic to determine whether a cachemiss rate is below a threshold, and in response to a determination thatthe cache miss rate is below the threshold. to identify one or moreleast recently used sections of a volatile memory module which are in amodified state, relocate data from the one or more least recently usedsections of the volatile memory module which are in a modified state,and power down the volatile memory module.

The electronic device may comprise logic to determine whether a cachemiss rate is below a threshold, and in response to a determination thatthe cache miss rate is not below the threshold, to activate at least oneinactive memory module.

The sections of volatile memory correspond to at least one of a cacheline, a memory chip, a memory rank, or a memory bank.

In example 4, a method to manage a memory system coupled to anelectronic device, wherein the memory system comprises a volatile memoryand a nonvolatile memory, comprises determining, in a controller,whether an electronic device is operating in a low power state, and inresponse to a determination that the electronic device is operating in alow power state, implementing a memory state management routine whichreduces power to at least a section of volatile memory in the memorysystem.

The method may further comprise identifying one or more sections ofvolatile memory which are in an invalid state, and suspending refreshoperations to the one or more sections of volatile memory in an invalidstate.

The method may further comprise identifying one or more sections of avolatile memory module which are in a modified state, relocating datafrom the one or more sections of a volatile memory module which are in amodified state, and powering down the volatile memory module.

The method may further comprise determining whether a cache miss rate isbelow a threshold, and in response to a determination that the cachemiss rate is below the threshold, identifying one or more least recentlyused sections of a volatile memory module which are in a modified state,relocating data from the one or more least recently used sections of thevolatile memory module which are in a modified state, and powering downthe volatile memory module.

The method may further comprise determining whether a cache miss rate isbelow a threshold, and in response to a determination that the cachemiss rate is not below the threshold, activating at least one inactivememory module.

The sections of volatile memory correspond to at least one of a cacheline, a memory chip, a memory rank, or a memory bank.

The terms “logic instructions” as referred to herein relates toexpressions which may be understood by one or more machines forperforming one or more logical operations. For example, logicinstructions may comprise instructions which are interpretable by aprocessor compiler for executing one or more operations on one or moredata objects. However, this is merely an example of machine-readableinstructions and embodiments are not limited in this respect.

The terms “computer readable medium” as referred to herein relates tomedia capable of maintaining expressions which are perceivable by one ormore machines. For example, a computer readable medium may comprise oneor more storage devices for storing computer readable instructions ordata. Such storage devices may comprise storage media such as, forexample, optical, magnetic or semiconductor storage media. However, thisis merely an example of a computer readable medium and embodiments arenot limited in this respect.

The term “logic” as referred to herein relates to structure forperforming one or more logical operations. For example, logic maycomprise circuitry which provides one or more output signals based uponone or more input signals. Such circuitry may comprise a finite statemachine which receives a digital input and provides a digital output, orcircuitry which provides one or more analog output signals in responseto one or more analog input signals. Such circuitry may be provided inan application specific integrated circuit (ASIC) or field programmablegate array (FPGA). Also, logic may comprise machine-readableinstructions stored in a memory in combination with processing circuitryto execute such machine-readable instructions. However, these are merelyexamples of structures which may provide logic and embodiments are notlimited in this respect.

Some of the methods described herein may be embodied as logicinstructions on a computer-readable medium. When executed on aprocessor, the logic instructions cause a processor to be programmed asa special-purpose machine that implements the described methods. Theprocessor, when configured by the logic instructions to execute themethods described herein, constitutes structure for performing thedescribed methods. Alternatively, the methods described herein may bereduced to logic on, e.g., a field programmable gate array (FPGA), anapplication specific integrated circuit (ASIC) or the like.

In the description and claims, the terms coupled and connected, alongwith their derivatives, may be used. In particular embodiments,connected may be used to indicate that two or more elements are indirect physical or electrical contact with each other. Coupled may meanthat two or more elements are in direct physical or electrical contact.However, coupled may also mean that two or more elements may not be indirect contact with each other, but yet may still cooperate or interactwith each other.

Reference in the specification to “one embodiment” or “some embodiments”means that a particular feature, structure, or characteristic describedin connection with the embodiment is included in at least animplementation. The appearances of the phrase “in one embodiment” invarious places in the specification may or may not be all referring tothe same embodiment.

Although embodiments have been described in language specific tostructural features and/or methodological acts, it is to be understoodthat claimed subject matter may not be limited to the specific featuresor acts described. Rather, the specific features and acts are disclosedas sample forms of implementing the claimed subject matter.

1. (canceled)
 2. A controller comprising logic to: determine whether anelectronic device comprising a volatile memory and a nonvolatile memoryis operating in a low power state; and in response to a determinationthat the electronic device is operating in the low power state,determine whether a cache miss rate is below a threshold; and inresponse to a determination that the cache miss rate is below thethreshold: identify one or more sections of the volatile memory that arein a modified state; relocate data only from the one or more sections ofthe volatile memory that are in the modified state; and power down theone or more sections of the volatile memory.
 3. The controller of claim2, wherein relocate data only from the one or more sections of thevolatile memory further comprises relocate data only from the one orsections of the volatile memory to a section of the volatile memory. 4.The controller of claim 2, wherein relocate data only from the one ormore sections of the volatile memory further comprises relocate dataonly from the one or more sections of the volatile memory to thenonvolatile memory.
 5. The controller of claim 2, wherein the volatilememory is dynamic random access memory (DRAM).
 6. The controller ofclaim 2, wherein the volatile memory is three dimensional (3D) crosspoint memory.
 7. The controller of claim 2, further comprising logic to:identify one or more sections of the volatile memory that are in aninvalid state; and suspend refresh operations to the one or moresections of the volatile memory that are in the invalid state.
 8. Thecontroller of claim 2, wherein the one or more sections of the volatilememory that are in the modified state further comprises one or moreleast recently used sections of the volatile memory.
 9. The controllerof claim 2, further comprising logic to: in response to a determinationthat the cache miss rate is not below the threshold, activate at leastone inactive section of the volatile memory.
 10. The controller of claim2, wherein the sections of the volatile memory correspond to at leastone of a cache line, a memory chip, a memory rank, or a memory bank. 11.The controller of claim 2, further comprising logic to arrange thevolatile memory such that read-only pages are located contiguously. 12.An electronic device, comprising: a volatile memory; a nonvolatilememory; and a controller comprising logic to: determine whether anelectronic device comprising a volatile memory and a nonvolatile memoryis operating in a low power state; and in response to a determinationthat the electronic device is operating in the low power state,determine whether a cache miss rate is below a threshold; and inresponse to a determination that the cache miss rate is below thethreshold: identify one or more sections of the volatile memory that arein a modified state; relocate data only from the one or more sections ofthe volatile memory that are in the modified state; and power down theone or more sections of the volatile memory.
 13. The device of claim 12,wherein relocate data only from the one or more sections of the volatilememory further comprises relocate data only from the one or sections ofthe volatile memory to a section of the volatile memory.
 14. The deviceof claim 12, wherein relocate data only from the one or more sections ofthe volatile memory further comprises relocate data only from the one ormore sections of the volatile memory to the nonvolatile memory.
 15. Thedevice of claim 12, wherein the volatile memory is dynamic random accessmemory (DRAM).
 16. The device of claim 12, wherein the volatile memoryis three dimensional (3D) cross point memory.
 17. The device of claim12, wherein the sections of the volatile memory correspond to at leastone of a cache line, a memory chip, a memory rank, or a memory bank. 18.The electronic device of claim 12, wherein the controller compriseslogic to arrange the volatile memory such that read-only pages arelocated contiguously.
 19. A method to manage a memory system coupled toan electronic device, comprising: determining, in a controller, whetheran electronic device comprising a volatile memory and a nonvolatilememory is operating in a low power state; and in response to determiningthat the electronic device is operating in the low power state,determining whether a cache miss rate is below a threshold; and inresponse to determining that the cache miss rate is below the threshold:identifying one or more sections of the volatile memory that are in amodified state; relocating data only from the one or more sections ofthe volatile memory that are in the modified state; and powering downthe one or more sections of the volatile memory.
 20. The method of claim19, wherein relocating data only from the one or more sections of thevolatile memory further comprises relocating data only from the one orsections of the volatile memory to a section of the volatile memory. 21.The method of claim 19, wherein relocating data only from the one ormore sections of the volatile memory further comprises relocating dataonly from the one or more sections of the volatile memory to thenonvolatile memory.
 22. The method of claim 19, further comprisingarranging the volatile memory such that read-only pages are locatedcontiguously.
 23. A computer program product comprising logicinstructions stored in a non-transitory computer readable medium that,when executed by a controller, configure the controller to performoperations to manage a memory state of a volatile memory, comprising:determining whether an electronic device comprising a volatile memoryand a nonvolatile memory is operating in a low power state; and inresponse to determining that the electronic device is operating in thelow power state, determining whether a cache miss rate is below athreshold; and in response to determining that the cache miss rate isbelow the threshold: identifying one or more sections of the volatilememory that are in a modified state; relocating data only from the oneor more sections of the volatile memory that are in the modified state;and powering down the one or more sections of the volatile memory. 24.The computer program product of claim 23, wherein relocating data onlyfrom the one or more sections of the volatile memory further comprisesrelocating data only from the one or sections of the volatile memory toa section of the volatile memory.
 25. The computer program product ofclaim 23, wherein relocating data only from the one or more sections ofthe volatile memory further comprises relocating data only from the oneor more sections of the volatile memory to the nonvolatile memory. 26.The computer program product of claim 23, further comprising logic toarrange the volatile memory such that read-only pages are locatedcontiguously.